Pii: S1359-6462(00)00590-x

As the trend in requirements of electronic packaging is toward higher I/O, greater performance, higher density, and lighter weight, the use of area array packaging technology is expected to increase. The type of packaging, such as ball grid array (BGA), chip scale package (CSP), and Flip Chip, provides the ultimate in high I/O-density and count with superior electrical performance, and very small size. The mechanical properties of solder joint are recognized as one of the critical factors that determine their reliability and lifetime [1–5]. During soldering, the formation of intermetallic compounds (IMCs) at solder/substrate interface is inevitable and ensures a good metallurgical bond. However, during storage and field service, the growth of IMCs will influence the strength of solder joints and result in mechanical failure of the joints [6–10]. Our recent research result shows that the fatigue lifetime of solder joint decreases linearly with the increasing square root of IMCs layer thickness [11]. Since the intermetallic is responsible for the solder joint failures, attention has to be paid to the effect of IMCs growth on the lifetime and reliability of microelectronic assemblies. This paper discusses the Ni-Sn/Cu-Sn IMCs layer growth kinetics in the joint soldered on plated Au/Ni FR-4 printed circuit board (PCB), which is one of the most commonly used substrate for fine pitch area array packaging. The kinetic model describing and predicting the IMC thickness can be used to estimate the solder joint reliability and lifetime, according the relationship of the IMC thickness with vibration fatigue failure and cyclic bend fatigue.